Systems Explore

Built a fully pipelined RISC-V CPU in Verilog across 6 phases, from assembler to caches. Each phase was validated against an autograder that compared execution traces to an ideal simulation.

My contributions spanned most of the stack: B-type instruction encoding in the assembler, the decoder module and full control unit (opcode-to-signal truth table), all four pipeline registers with stall and flush support, and the shared main memory module with a miss-handling FSM covering dirty write-back, prefetch, and a 100-cycle memory penalty.

Installed a minimal Arch system to get a better feel for how an OS actually comes together. Learned a lot about bootloaders, filesystems, displays, networking, and recovery through maintenance and installations.

Wrote bash scripts to automate display setup, brightness control, and switching between network services. These helped me learn new tools, simplify systemd tasks, and customize my environment beyond what Windows allows.